Hallo Everyone

So i have simulink block where i input a sine wave of 44.1 kHz and the using three stages of FIR Interpolation block from Simulink (1st stage 32, 2nd Stage 2, 3rd Stage 2, 4th Stage 2 upsamples) i get the output to 11.2 MHz. Then used the HDL coder to generate the synthesized HDL code, the problem is with the Fmax (Maximum frequency at which the circuit can be clocked). My Fmax is only at 27.9 MHz. For the setup in the HDL coder i choose a Generic ASRIC or FPGA and then choose a cyclone processor. Any idea how to set the clock in the HDL coder to get a higher Fmax Or should i change some settings in the simulink solver, there i have a setting for discret fixed step solver with an auto step size.